DESCRIPTION:
When updating the operating system, always update to the latest version available for the product and its respective order number. The previous versions of the operating system are only intended as backup to allow a downgrade to the original version. Until now this is not known to have been necessary in any case.
The respective latest version of a CPU operating system is valid for all versions of that order number.
Please note:
During the firmware update the actual values will be lost. If you require them, please save these values before starting with the FW update with the function "Copy RAM to ROM...."
The update can either be performed via Micro Memory Card or online:
Micro Memory Card:
Requirements for creating an operating system update card:
- Micro Memory Card with at least 8 MB storage capacity order number 6ES7953-8LP20-0AA0
- STEP 7 V5.1 SP2 or higher
- PC with external PROM programmer 6ES7792-0AA00-0XA0 or FieldPG for programming the Memory Card
Creating the operating system update card with STEP7:
- Download the desired CPU file
- Unpack the file by double-clicking the file name
- Delete the Micro Memory Card by executing: "File/S7 Memory Card/Delete" in Simatic Manager.
- Program the operating system by selecting "Update target system/operating system" in SIMATIC Manager,
then select the target directory and "open" the CPU_HD.UPD file to start the programming process.
- Programming of the operating system update card is completed when the message "The firmware update for the module with the order number 6ES7315-2FJ14-0AB0 was transferred successfully to the S7 memory card" appears on the screen.
To update the operating system:
- Switch OFF the power supply (PS) of the rack in which the CPU is located
- Isolate the PLC from the communication network
- Insert the prepared operating system update card into the CPU
- Switch ON the power supply (PS) for the rack in which the CPU is located
- The operating system is transferred from the Micro Memory Card to the internal CPU flash EPROM. during this process, all indicator LEDs on the CPU are lit (FRCE, RUN, STOP, SF, BF).
- The operating system update is completed after about 2 minutes and is indicated by slowly blinking STOP LED => prompt for overall reset by the system
- Switch OFF the power supply (PS) and insert the Micro Memory Card intended for operation.
- Switch ON the power supply; the CPU automatically performs an overall reset and is then immediately operational.
- Before connecting the PLC to the communication network again the clock must be synchronized.
2. Online:
Requirements:
- An online update of the firmware is possible with STEP 7 V5.3 or higher3.
- The module in the station whose firmware is to be updated must be accessible online.
- A MMC (Micro Memory Card) must be available in the module as buffer memor.
- The unpacked files with the current firmware version must be present in the file system of your PG or PC. A folder must only contain the files of one firmware version.
To update the firmware:
- Start STEP 7 and switch to HW-Config.
- Open the station with the CPU to be updated.
- Earmark the CPU.
- Select the command "PLC > Update firmware". The command can only be activated, if the highlighted CPU supports the function "Update Firmware".
- In the dialog "Update Firmware" use the "Find" button to select the path to the firmware update files (*.UPD).
- Once you have selected a file, information about the module suitable for the file and the firmware version required is shown in the lower portion of the dialog "Update Firmwaree"
- Click on the "Execute" button. STEP 7 will check whether the selected file can be interpreted by the module; if the answer is positive, the file will be loaded into the CPU. If the operating mode of the CPU must be changed for this, you will be prompted via dialogs. The CPU will then autonomously perform the firmware update.
- Check with STEP 7 (read diagnostic buffer of the CPU), whether the CPU successfully starts up with the new firmware.
Please note
After the CPU has been subjected to an overall reset, the following values will be retained:
- the parameters of the MPI interface (MPI address and highest MPI address)
- the IP address of the CPU
- the sub-network screen
- the static SNMP parameters
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Overview of order numbers and latest versions of the CPU 315F-2 PN/DP:
| Update V3.2.8 (6ES7315-2FJ14-0AB0) |
The above CPU version contains no new functions.
Note on STEP7 dependencies and upward compatibility:
To be able to run this CPU your require STEP7 V5.5 or higher.
For CBA configuration you require iMap V3.0 +SP1 or higher.
Configurations with earlier STEP7 and iMap versions can be used with upward compatibility.
For failsafe applications you require the option package S7 Distributed Safety V5.4 SP1 or higher.
Firmware update V3.2.8 provides the following corrections:
- COS values of very small numbers (>=0 and <3.8518597E-34) are now output correctly with value 1.
- AUF DB/DI indirect no longer causes sporadic opening of an incorrect DB.
- In the case of a block upload or download the CPU will no longer sporadically go to Defect with Z1=F01A.
- Communication abortions while the communications functions are running will no longer sporadically lead to Defect with Z1=F012.
- In the case of block calls of the SFCs 82..84 with REQ=0 (RET_VAL=7000), BUSY will not be signaled with TRUE anymore.
- The accuracy of the square root calculation "SQRT" has been improved.
| Update V3.2.7 (6ES7315-2FJ14-0AB0) |
This firmware version contains the following new features:
- SFC 109 PROTECT: new mode 12, with which protection level 3 can be activated via user program without password legitimation (even with a password it is now impossible to read/write access the CPU)
see also Product Information at entry ID 61757603
Note on STEP7 dependencies and upward compatibility:
To be able to run this CPU your require STEP7 V5.5 or higher.
For CBA configuration you require iMap V3.0 +SP1 or higher.
Configurations with earlier STEP7 and iMap versions can be used with upward compatibility.
For failsafe applications you require the software option S7 Distributed Safety Version V5.4 SP1 or higher.
Firmware update V3.2.7 provides the following corrections:
- To prevent loss of retentivity with event ID 16# 4580 resp. event ID 16# 6523, the MMC connection in the case of power off/on has been optimized.
- If the SFC 23 DEL_DB is used and a DB does not exist, defect Z1=F833 will no longer occur.
- In the case of synchronization errors that cause a STOP of the CPU, defect Z1=F004 will no longer occur highly sporadically.
- The abortion of a block transfer will no longer lead to a sporadic defect Z1=4131.
- Connections of the CPU to a PLC link device will now be cut completely in the case of a connection abortion.
- If clock flags are used, the three adjacent flag byte addresses are no longer influenced anymore.
- Uploading of blocks to programming devices has been performance optimized.
- Hardware releases (with boot loader A25.7.5 and below) now always permit the loading of blocks that were encrypted with Block Privacy.
- Specific resources have been increased to ensure that Web-server accesses in the case of storm attacks remain operable.
- If I-Devices have been configured with sub-module lengths of more than 32 Bytes, OB61 clock pulses will no longer be inaccurate or fail altogether.
- If programs have been created with SCL, TSEND or TRECV blocks on which send or receive buffer lenghts have been declared as STRING, will no longer cause RET_VAL 807F.
- Upstream switches that do not support LLDP will no longer cause a defect with Z1=8005 if there are several adjacent modules.
- After connection breaks with the Open-User communication there will be no more highly sporadic defect with Z1=E801.
- When reading out the data of an I-slave with several subslots by means of SFC14, error code 80A0: "An access error has been identified during I/O access" will no longer come up.
- If a devices fails, the inputs of the device which are included in the process I/O image of the controller will reliably be set to 0.
- In the case of a large number of simultaneous events on the DP line (station failure, station return, diagnostics, etc.), the highly sporadic defect Z1=E802 will no longer occur.
- The CPU will no longer go to defect with Z1=F012 if "http://IP-Adresse/Portal/Portal.mwsl" is entered in the browser.
- Multiple bit logical interconnections that concern the same byte will now be executed correctly.
- Downloading of blocks or projects will no longer cause the cycle time to be constantly increased therafter.
| Update V3.2.6 (6ES7315-2FJ14-0AB0) |
The above new CPU version does not contain any new functions.
Note on STEP7 dependencies and upward compatibility:
To be able to use the new functionalities your require STEP7 V5.5 or higher.
For CBA configuration you require iMap V3.0 +SP1 or higher. Configurations with earlier STEP7 and iMap versions can be used with upward compatibility.
For failsafe applications you require the optional package S7 Distributed Safety V5.4 + SP1 and higher.
Firmware update V3.2.6 provides the following corrections:
- Modules that have run for approx. 500 days will no longer get stuck sporadically or show endlessly running timers.
- Cache errors that cannot be corrected and very sporadically occur during CPU startup will now be entered in the diagnostic buffer with defect identifier Z1= F001 and branched to "Defect" status. During startup the CPU can no longer enter a inconsistent state which is sporadically entered in the diagnostic buffer with event ID 16# 4580 (inconsistent backup buffer content).
| Update V3.2.3 (6ES7315-2FJ14-0AB0) |
The above CPU version contains a number of new functions which are described at entry ID 46119963.
Note on STEP7 dependencies and upward compatibility:
To be able to use the new functionalities your require STEP7 V5.5 or higher with HSP 0199.
For CBA configuration you require iMap V3.0.1 or higher.
Configurations with earlier STEP7 and iMap versions can be used with upward compatibility.
Distributed Safety:
For failsafe applications you require the optional package S7 Distributed Safety V5.4 + SP1 and higher.
Firmware update V3.2.3 provides the following corrections:
- No more sporadical loss of actual values after power OFF due to a request for overall reset because of a memory replacement (event ID 16# 6526)
- The retentivity backup for power OFF has been stabilized (concerns highly sporadical loss of retentivity with event ID 16# 4580 "Backup buffer content inconsistent").
- Adding a step in S7-Graph and subsequent block download no longer leads to a length-of-area error for one cycle. With immediate effect, several blocks can be included together in the chain again.
- If a slave gives a negative response to the first data message frame of the master (e.g. with "have no memory space for data response“), this will not prevent the slave from being included at a later point in time.
- If a slave has been activated with the SFC12 and subsequently fails, the OB86 will be called again when the slave returns to the DP line. Furthermore, when the slave returns during a transition from STOP to STARTUP (e.g. during startup of the CPU), the identifier for an I/O access error will not sporadically remain set.
- The command sequence "L FW 2, TAK, T FW 3, TAK" will now also work if the areas of "T" and "L" are overlapping (as shown in the named command sequence).
- Configured but non-existing PA inputs can now be controlled with VAT again.
- The configuration of a Profinet connection without devices will no longer cause the BF2 LED to be lit after the download.
- The STL instruction DTB "DWord-To-BCD" will no longer lead to a defect with Z1=f11c if the input value is invalid (no BCD value).
- A SDB0 with invalid baud rate will no longer lead to a defect with Z1=914A; instead, the MPI default baud rate of 187.5 kBd will now be preset.
- Power OFF during online monitoring of blocks will not sporadically lead to a defect with Z1=0019 or Z1=F104.
- From now on the SFC1 "READ_CLK" will convert the year correctly to a BCD number. Subsequent instructions that are based on the BCD format (e.g. BTI "BCD-To-Integer") will thus no longer lead to conversion errors (e.g. event ID 16# 2521 "BCD conversion error").
| Update V3.1.1 (6ES7315-2FJ14-0AB0) |
The above new CPU version does not contain any new functions.
Note on STEP7:
To operate this CPU you require V5.4 SP4 or higher with HSP 0189. To be able to use the new WEB features you require V5.4 SP5 with HSP 0189 or higher.
For CBA configuration you require iMap V3.0.1 or higher.
Configurations with earlier STEP7 and iMap versions can be used with upward compatibility.
Distributed Safety:
For failsafe applications you require the optional package S7 Distributed Safety V5.4 and higher.
Firmware update V3.1.1 will result in the following corrections:
- If a slave is no longer accessible, e.g. because the bus cable has been disconnected, its Process Input Image Register on the CPU will now safely switch to false.
- Reading 4 bytes with the SFC14 will now also supply the correct values for the last 2 bytes.
- Deletion and creation of a DB with the same number by means of SFC "Delete DB" and "Create DB“ can now be done in the same cycle.
- Data type Character can now also be used for ANY-Pointer in the SFBs 52 and 53.
- Uploading of firmware versions is no longer aborted with message 13:4759 "The firmware was not accepted by the module".
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