In the STEP 7 programming languages ladder diagram (LAD) and function block diagram (FBD), compilation errors might occur when using an FM352-5.

The information below is for LAD and FBD.
It is recommended to use the solutions given below in multiple networks.

• LAD solution
• FBD solution

Note:
If you are working in Debug mode, all the examples will be processed correctly. This is because the program does not run on the FM352-5 module, but on the CPU memory.

Validity:
The compiler behavior will be cleared in the next release version of the Programming Tools V1.2.1.0.

LAD solution
Compiling errors can occur if you make an OR link directly from the bus bar with one or multiple nested sublogic circuits.

Fig. 01: OR link with nested logic in second sequence

There is a fault in the network compilation because the nested sequence comes second (2).
The compiler makes an OR link for the result of the first sublogic (1) with contact #Din[0] instead of the result of the second sublogic (2).

Remedy by nested logic at the beginning of a network
In order to avoid compilation faults, you program the nest sublogic (3) first and then the non-nested sublogic (4).

Fig. 02: OR link with simple logic in second sequence

Since sequence 4 is a simple link, the correct result of the OR link of sequences 3 and 4 is output after compilation.

Remedy by splitting into separate networks (preferred solution)
If possible, you should move the sequences into separate networks to avoid compilation faults in general.

Fig. 03: Network 1

Fig. 04: Network 2

Fig. 05: Network 3

Since sequences 5 and 6 are in different networks, the logic is compiled correctly. The logic in sequence 7 is now a simple OR link and is compiled without errors.

FBD solution
Compiling errors can occur if you make an OR link with one or multiple nested sublogic circuits.

Fig. 06: OR link with nested logic in second sequence

There is a fault in the network compilation because the nested sequence comes second (2).
The compiler makes an OR link for the result of the first sublogic (1) with input #Din[0] instead of the result of the second sublogic (2).

Remedy by nested logic at the beginning of a network
In order to avoid compilation faults, you program the nest sublogic (3) first and then the non-nested sublogic (4).

Fig. 07: OR link with simple logic in second sequence

Since sequence 4 is a simple link, the correct result of the OR link of sequences 3 and 4 is output after compilation.

Remedy by splitting into separate networks (preferred solution)
If possible, you should move the sequences into separate networks to avoid compilation faults in general.

Fig. 08: Network 1

Fig. 09: Network 2

Fig. 10: Network 3

Since sequences 5 and 6 are in different networks, the logic is compiled correctly. The logic in sequence 7 is now a simple OR link and is compiled without errors.