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Operating System Updates for CPU 314C-2 DP
Part number:

DESCRIPTION:
When updating the operating system, you should always update to the latest version available for the product with the relevant order no. The previous versions of the operating system are just meant to be a backup to enable you to downgrade to the original version. Until now this is not known to have been necessary in any case.
The latest version of a CPU operating system is always valid for all the versions of that order no..

The update can be performed either with a Micro Memory Card or online:

1. Micro Memory Card:

Requirements for creating an operating system update card:

  • Micro Memory Card with at least 4 MB storage capacity
    (order number 6ES7953-8LM20-0AA0)
  • STEP 7 V5.1 or higher
  • PC with external PROM programmer (6ES7 792-0AA00-0XA0) or 
    PG720 / 740 with adapter (6ES7 798-0BA00-0XA0) or
    FieldPG / PowerPG  for programming the Memory Card

Creating an operating system update card with STEP7:

  1. Download the desired CPU file.
  2. Unpack the file by double-clicking the file name
  3. Delete the Micro Memory Card by executing: "File/S7 Memory Card/Delete" in Simatic Manager.
  4. Program the operating system by selecting "Update target system/operating system" in SIMATIC Manager, then select the target directory and "Open" the CPU_HD.UPD file to start the programming process.
  5. Programming of the operating system update card is completed when the message "The firmware update for the module with the order number 6ES7 314-6CG03-0AB0 was transferred successfully to the S7 memory card" appears on the screen.

To update the operating system:

  1. Switch OFF the power supply (PS) of the rack in which the CPU is located 
  2. Isolate the PLC from the communication network
  3. Insert the prepared operating system update card in the CPU
  4. Switch ON the power supply (PS) for the rack in which the CPU is located
  5. The operating system is transferred from the Micro Memory Card to the internal CPU flash EPROM. During this time all the CPU's LEDs will be on (FRCE, RUN, STOP, SF, BF).
  6. The operating system update is completed after about 2 minutes and is indicated by slow flashing of the STOP LED on the CPU => prompt for overall reset by the system
  7. Switch the power OFF at the power supply and insert the Micro Memory Card required for operation.
  8. Switch ON the power supply. The CPU automatically does an overall reset and is then immediately ready for operation.
  9. Before connecting the PLC to the communication network again the clock must be synchronized.

2. Online:

Requirements:

  • Online updating of the firmware is possible with STEP 7 V5.3 and higher.
  • The module in the station whose firmware is to be updated must have firmware version V2.6.1 or higher and be accessible online.
  • The module status of the CPU can be checked with STEP7 in the online mode. Version A0.21.0 or higher must be displayed to be able to perform the firmware update.

    Select: SIMATIC Manager -> <Name of station> -> Strg+D


    Fig 1: Module status

  • The module must be listed with firmware version V2.6 in the Hardware Configuration in SIMATIC-Manager.
  • A MMC (Micro Memory Card) must be inserted in the module as buffer memory.
  • The unpacked files with the latest firmware version must be available in the file system of your PG or PC:

    BG_ABL.UPD
    CPU_HD.UPD
    KOMP_1.UPD

    Any one folder may only contain the files for one firmware version.

To update the firmware:

  1. Start STEP 7 and switch to HW-Config.
  2. Open the station with the CPU to be updated.
  3. Earmark the CPU.
  4. Select the command "Target system > Update firmware". The command can only be activated, if the marked CPU supports the function "Firmware update".
  5. In the opened dialog "Update firmware" now use the "Search" button to find the path to the firmware update files (*.UPD).
  6. When you have selected a file, information will come up in the lower part of the "Firmware update" dialog, for which module and as from which firmware version the file is valid.
  7. Click the "Execute" button. STEP 7 will check whether the selected file can be interpreted by the module and then load the file to the CPU if the answer is positive. If the operating mode of the CPU must be changed for this purpose, you will be prompted via dialogs. The CPU will then execute the firmware update by itself.
  8. Check with STEP 7 (read diagnostic buffer of the CPU), whether the CPU successfully starts up with the new firmware.

Overview of order no.’s and latest versions of the CPU314C-2 DP:
Order No.

FW
version

Upgrade with ...
6ES7 314-6CG03-0AB0    
 

V2.6.11

Recommended for upgrading:

Update V2.6.11 description

 3146CG03_V2611.EXE ( 970 KB )

 

V2.6.9

For backup only:

Update V2.6.9 description

 3146CG03_V269.EXE ( 970 KB )

 

V2.6.6

For backup only:

Update V2.6.6 description

 3146CG03_V266.EXE ( 969 KB )

 

V2.6.4

For backup only:

Update V2.6.4 description

 3146CG03_V264.EXE ( 968 KB )

 

V2.6.3

For backup only:

Update V2.6.3 description

 

V2.6.1

For backup only:

Update V2.6.1 description

 

V2.0.12

For backup only:

 3146CG03_V2012.EXE ( 885 KB )

     
6ES7 314-6CF02-0AB0    
 

V2.0.12

Recommended for upgrading:

Update V2.0.12 description

 3146CF02_V2012.EXE ( 885 KB )

 

V2.0.11

For backup only:

Update V2.0.11 description

 3146CF02_V2011.EXE ( 880 KB )

 

V2.0.10

For backup only:

 3146CF02_V2010.EXE ( 880 KB )

     
6ES7 314-6CF01-0AB0    
 

V2.0.11

Recommended for upgrading:

Update V2.0.11 description

 3146CF01_V2011.EXE ( 880 KB )

 

V2.0.10

For backup only:

Update V2.0.10 description

 3146CF01_V2010.EXE ( 880 KB )

 

V2.0.8

For backup only:

Update V2.0.8 description

 3146CF01_V208.EXE ( 876 KB )

 

V2.0.5

For backup only:

 3146CF01_V205.EXE ( 880 KB )  

     
6ES7 314-6CF00-0AB0    
 

V1.0.5

Recommended for upgrading:

Update V1.0.5 description

 3146CF00_V105.EXE ( 813 KB )  

 

V1.0.3

For backup only:

Update V1.0.3 description

 3146CF00_V103.EXE ( 807 KB )  

 

V1.0.2

For backup only:

Update V1.0.2 description

 3146CF00_V102.EXE ( 807 KB )  

.

V1.0.0

For backup only:

 3146CF00_V100.EXE ( 807 KB )  

Update V2.6.11 (6ES7 314-6CG03-0AB0)

The above CPU version does not contain any new functions.

Note on STEP7:
To operate this CPU you require STEP7 V5.4 + SP3 or STEP7 V5.3 + SP2 with HSP 0123 or higher.

Firmware update V2.6.11 provides the following corrections:

  • After power ON there will be no more sporadical loss of actual values after overall reset with Event ID 16#6522 or 16#4580 ( backup buffer inconsistent ).
  • No more sporadical Defect Z1=97EA when monitoring blocks or variables with simultaneously connected HMI devices.
  • If a DB is available, the SFC 24 "TEST_DB" will now always supply the correct length of the DB, irrespective of the latter's memory attribute or SFC83 called in parallel.
  • When putting the clock forward, the weekday ( variable "OB10_DATE_TIME" ) will now be adjusted immediately in the local data of the OB10.

Update V2.6.9 (6ES7 314-6CG03-0AB0)

The above CPU version does not contain any new functions.

Note on STEP7:
To operate this CPU you require STEP7 V5.3 + SP2 + HSP 0123 or STEP7 V5.4 + SP3 or higher.

Firmware update V2.6.9 provides the following corrections:

  • Loss of actual value during operation with event code 16#6523 and Z2=8020 / Z3=1410 now prevented.
  • Forcing will no longer result in a loss of timed interrupts.
  • Fast scrolling when monitoring blocks or variables tables no longer causes Defect Z1=6A6F.
  • Incorrect length specifications of ANY Pointers for SFCs 20 and 21 will now result in BLF (Length-of-Area Error: 8x22 or 8x23); this prevents follow-up errors such as cycle time exceeded and watchdog.
  • In the case of communication problems with external HMI systems e.g. ProSCADA, or when using a CP343-1EX11, Defect Z1=98C6 will no longer occur

Update V2.6.6 (6ES7 314-6CG03-0AB0)

The above CPU version does not contain any new functions.

Note on STEP7:
To operate this CPU you require STEP7 V5.3 + SP2 with HSP 0123 or higher.

Firmware update V2.6.6 provides the following corrections:

  • If the connection is aborted during cyclic HMI reading, the CPU will no longer enter defect mode Z1=7173.
  • Routing problems with the CP5613 A2 have been corrected.
  • Soft keys assigned to bit variables in an OP3 will now set the assigned bit in the PLC if the key is pressed.
  • Forcing of inputs (PAI) is now always effective also in alarm OBs.
  • Communication with HMI devices has been speeded up.
  • If the connection is aborted during monitoring of blocks or variables, defect Z1=7393 will no longer occur.
  • If the error message "The memory space on the module is insufficient. Should the loading memory be compressed?" comes up when uploading software blocks, the acknowledgement with "Yes" no longer remains ineffective.
  • If blocks FB48 and FB49 ("Signal system errors") are loaded, DEFECT  Z1=FFFF will no longer occur after program loading and voltage off/on.

Update V2.6.4 (6ES7 314-6CG03-0AB0)

The above CPU version does not contain any new functions.

Note on STEP7:
To operate this CPU you require STEP7 V5.3 + SP2 with HSP 0123 or higher.

Firmware update V2.6.4 provides the following corrections:

  • The callup parameters of SFBs 52, 53, 75, 81 and SFCs 11, 51, 55-59 will only be checked if the REQ bit has been set. If the REQ bit has not been set, RET_VAL will not signal an error anymore.
  • An address offset of > 4096 bytes on the ANY Pointer of parameters SRCBLK or DSTBLK of the SFCs 82/83/84 will no longer lead to the checkback signal 8x22 on RET_VAL.
  • Loading the SDBs from the STEP7 block container will no longer lead to STOP because of a configuration inconsistency.
  • The CPU correctly enters STOP mode because of a missing slave, if the configuration bit "Start-up if desired configuration equals actual configuration" is not set. If the bit "Startup if desired configuration equals actual configuration" is subsequently set and the configuration post-loaded to the CPU, the latter will now start-up.
  • In the case of a block comparison in the online view of the block list, all blocks will now be shown and not only the first 50 blocks of each type.
  • SFBs 52, 53 and 81 will no longer deliver Retval 8x3a if data type BLOCK_DB has been entered in the Parameter Record.
  • Connection establishment to operator panels has been improved.

Update V2.6.3 (6ES7 314-6CG03-0AB0)

The above CPU version does not contain any new functions.

Note on STEP7:
To operate this CPU you require STEP7 V5.4 + SP3 or STEP7 V5.3 + SP2 with HSP 0123 or higher.

Firmware update V2.6.3 results in the following corrections:

  • RLO corruption with “O“ operation (OR before AND function) in programmer operation with block status has been corrected.

Due to a problem with firmware V2.6.1 and V2.6.2, a corruption of the RLO could occur during operation with a programming device and online monitoring of block status, with the following program sequence:
A a b.c
A d e.f
.
.
A x y.z
O // the RLO thus formed could be corrupted (only during block status monitoring of this sequence)
A y z.x
.
.
A s t.u

  • If an addressed bit is set at input SD of SFCs 17, 18, 107 and 108, the complete byte will not be set to zero.
  • The data types Word and DWord are now also permitted with the RECORD parameter of SFBs 52 and 53

Update V2.6.1 (6ES7 314-6CG03-0AB0)

The above CPU version includes the following new functions:

  • Identification and maintenance data of the CPU (e.g. plant and location code)
  • Reset of the CPU to its delivery status
  • Online firmware update via network
  • Measuring initiator for Diagnostic Repeater (SFC 103 "DP_TOPOL") *
  • Extension of the block-related messages (SFC 105-108) *
  • Change of protection stage with SFC 109 "PROTECT“ *
  • SFC 64 "TIME_TCK" with 1 ms separation *
  • New software blocks SFC 70 "GEO_LOG", SFC 71 "LOG_GEO" and SFB 81 "RD_DPAR" *
  • Cycle duration measurement  
  • Clock synchronization via PROFIBUS DP 
  • Changed response of the CPU as clock master on MPI and DP interfaces;
    see Product Information or entry ID 25323411

* You will find detailled information on the additions to the various SFCs in the Operations List and the System Software Reference Manual for S7-300/400, System and Standard Functions.

Note on STEP7:
To operate this CPU, you require STEP7 V5.4 + SP3 or STEP7 V5.3 + SP2 with HSP 0123 or higher.

The following changes will become effective with firmware update V2.6.1:

  • If cyclic HMI reading is aborted, defect Z1:72C1 will now be prevented.
  • Copy functions (in particular with SCL programming) with parameters of the typ ANY STRING will now copy the exact no. of data contained in the length specification.
  • Copy functions with parameters of the type ANY will now also permit area code #85 and the RETVAL of the SFC83 will no longer display #8525 "Area error with writing".
  • When monitoring with callup path it is now possible to specify up to 7 blocks for the callup environment.
  • Loading of projects with CP or FM modules in which the MPI address of the CPU has been changed, no longer causes the error message "Station cannot be reached".

Update V2.0.12 (6ES7 314-6CF02-0AB0)

The above CPU version does not contain any new functions.


Note on STEP7:

To operate this CPU you require STEP7 V5.2+SP1 or higher.

Firmware update V2.0.12 results in the following corrections:

  • Defect  Z1:E802 in the case of OB request error and simultaneous high alarm load
    An OB request error (caused by long alarm processing time) will no longer lead to Defect when the load by other alarms is high at the same time.
  • Defect  Z1:72F1, or non-operable MPI, if several variables tables are monitored simultaneously
    If more than four variables tables are activated at the same time, the message "(8304): No further simultaneous upload process possible. There is a resource bottleneck" will be generated, and not a Defect.
  • Communication problems with the CP340: CP gets stuck during sending
    Communication with the CP has been improved.
  • Module remains up with a fault in HW Config
    After a corrected encoder short circuit on a DPV1 slave, the “faulty“ symbol in the configuration will now be removed.

Update V2.0.11 (6ES7 314-6CF01-0AB0)

The above CPU version does not contain any functional changes.

Note on STEP7:
To operate this CPU, you require STEP7 V5.2+SP1 or higher.

Firmware update V2.0.11 will result in the following changes:

  • Problems when calling the SFC58/59 with BUSY
    In the case of RET_VAL=7000h the BUSY bit will now be deleted correctly. 
  • Alarm_SQ messages will not be displayed in the case of a Runtime Start
    After a cold restart of WinCC-Runtime all the Alarm_SQ messages previously generated by a controller will be displayed in the WinCC AlarmControl. 
  • OB Request error after a clock interrupt
    A clock interrupt will now be earmarked for the next interrupt point in the future, if that interrupt time coincides with the current time.
  • Defect Z1:F102 after power ON
    The response in the case of power ON has been stabilized.
  • STOP event 16#6522 after power ON
    The response in the case of power ON has been stabilized

Update V2.0.10 (6ES7 314-6CF01-0AB0)

The above CPU version contains the following functional improvement:

    The number bands of FCs and FBs have been increased to 2048.

Note on STEP7:
To use this CPU, you require STEP7 V5.2+SP1 or higher.

Firmware update V2.0.10 corrects the following problems:

  • Defect Z1:64D2 after a connection break.
    If there is a connection break while a communication function „ Status Block“ or „Status/Force Variable“ is running, the connection will now be released correctly and a Defect will no longer occur.
  • Defects Z1:7015 and Z1:7010 after a connection break.
    If there is a connection break while the communication function „ Block Information“ is running and the CPU contains more than 51 blocks of a type (DB, FB or FC), the connection will now be released correctly and a Defect will no longer occur. 
  • Messages of the ALARM_SQ after down/up of WinCC cannot be acknowledged.
    When a ALARM_SQ message comes up while the HMI is not available, and the HMI is later activated again, the acknowledged message will now be deleted from the update memory. 
  • No difference in the OB100_STRT_INFO between switch in RUN and power ON
    The start info of the OB 100 will now indicate the correct type of startup. 
  • Defect Z1:7350 in the case of a cyclic access of an OP to a DB that is non-existent or too small.
    Area pointers on an OP, that refer to a DB which is non-existent or too small, will no longer cause a Defect of the CPU. 
  • PZF will be set after writing DS1 on BUS1* ASIC module
    If the SFC55 is used to write a DS1 on certain, non-parameterizable modules (modules with BUS13 ASIC or BUS1* ASIC), the PZF will no longer be set for this module and the module will still remain accessible even after the SFC call. 
  • No BF LED after a master failure / outputs will possibly not be deactivated.
    When used as passive i slave behind a repeater, with no further active station in this bus segment, and a fault occurs or a cable is unplugged, the master failure will now be signalled and the i slave will deactivate its outputs.
  • Diagnostic buffer entry "Module fault" with DPV1 slaves does not disappear.
    Two successive channel diagnostics from different slots of a DPV1 slave, that are both entered correctly in the diagnostic buffer, will no longer be displayed as faults after both channel diagnostics have been corrected one after the other.

Update V2.0.8 (6ES7 314-6CF01-0AB0)

The CPU version does not contain any significant functional changes.

Note on STEP7:
To use all the functions available up until now, you require STEP7/V5.1+SP4.
The configurations for the corresponding predecessor CPUs are upwardly compatible.

Firmware update V1.0.8 corrects the following problems:

  • In the case of a DEFECT of the CPU, the on-board analog I/Os are not switched off.
    Now, the on-board analog I/Os as well as the other I/O modules are switched off in the case of a DEFECT of the CPU.
  • Error 6523 "Request for overall reset due to MMC access errorr" after RAM-to-ROM
    Now, post-loading of data blocks after the function RAM-to-ROM no longer causes a request for overall reset with error entry 6523.
  • "Source and target block are identical" would lead to a coordination error (80C0) with the SFCs 83 and 84.
    Now, when calling the SFCs 83 and 84 the source and the target block can be selected to be  identical.
  • Sporadic RETVAL 80C4 with SFC59.
    Resource administration of the SFC59 "RD_REC" has been improved.
  • Defect FFFF in the case of repeated registration for process error diagnostics.
    Even repeated registration for process error diagnostics will no longer cause defect FFFF.
  • Incorrect status display before a loop.
    Display of the loop status data is now correct.
  • Load user program --> CPU goes to overall reset.
    Loading the user program no longer causes error message "(8404) S7 Protocol: The function cannot be executed" and thus also not to a request for overall reset of the CPU.
  • CPU Defect 3324 with STOP/RUN if SFB52/53 is running.
    STOP/RUN of the CPU if SFB52/53 is running no longer causes Defect 3324.
  • DEFECT 9862 after repeated unplugging and plugging of the Profibus connector.
    Now, if one repeatedly removes and returns the Profibus connector (e.g. simulates a loose contact) the CPU will no longer enter DEFECT mode.
  • DEFECT e800 when loading the SDBs
    When post-loading a changed configuration now, the CPU will no longer enter DEFECT mode.
  • If the IM151-1 HF is configured as DPV1 slave, the PZF will remain set for diagnostic addresses.
    Now, if the IM151-1 HF (6ES7 151-1BA00-0AB0) is configured as DPV1 slave, the power module and packed modules will get a diagnostic address. The PZF will no longer be set this diagnostic address.
  • Defect F102 after switching on an I slave with a very short runup time.
    Now, the CPU will no longer enter DEFECT mode in the case of a configuration-dependent very fast runup of an I slave.
  • RET_VAL 8010 with FC10 and FC11 when the CPU is a DP slave
    After switching the master to RUN, the FCs 10 and 11 from the PROFInet system library will now provide the correct RET_VAL=0.

Update V1.0.5 (6ES7 314-6CF00-0AB0)

The CPU version does not contain any significant functional changes.

Note on STEP7:
To use all the functions available up until now, you require STEP7/V5.1+SP4.
The configurations for the corresponding predecessor CPUs are upwardly compatible.

Firmware update V1.0.5 corrects the following problems:

  • Sporadic Defects F402 AND F204 after COMPRESSING
    No more defects will now occur after compressing.
  • PA enable will completely transfer the last process I/O image to the I/Os
    When using the function PA enable now, the outputs of the centralized racks will no longer assume their last value; Now, they will be reset or given a substitute value.
  • When deactivating the function PA enable, modules parameterized with "Hold last value" will be reset
    Deactivating the function PA enable now ensures that modules parameterized with "Hold last value" and not forced beforehand, assume their last value.
  • Sporadic Defect F834 after terminating HMI tasks
    Terminating HMI tasks now will no longer result in a Defect.
  • Sporadic Defect 98C1 when using an Applicom driver card
    Applicom driver cards can now be used without any problems.
  • Cycle time fluctuations when using the LOOP command
    Using the LOOP command no longer results in cycle time fluctuations.
  • In the case of periodic processing of the system function SFC 39 "DIS_IRT", alarm events that should be blocked, are enabled for short periods
    Periodic blocking of alarm events is now possible without any problems.
  • In the case of a failure of a standard slave, a non-involved input module would signal PZF
    When using standard slaves (CPU is DP master), where the available user data slots begin with slot 1 and slot 2 is configured as an output, a failure of this slave will no longer result in an I/O access error being signalled for a non-involved input module (or address), if the latter has the same input address as the output on slot 2 of the slave described above.
  • Defect 7089 in the case of an on-line selection from HW-Config (or HW-Diagnostics) when using slaves with a large no. of configured slots
    Even when using slaves with a large no. of configured slots (120 to 244), the on-line mode can now be selected from HW-Config or a HW-Diagnostics carried out, without any problems.
  • Error in the operating mode "Inching" and direction change with a CPU314C-2DP
    A direction change within one cycle in the operating mode "Inching" is now possible and no longer causes the CPU to continue in the previous direction.

Update V1.0.3 (6ES7 314-6CF00-0AB0)

The CPU version does not contain any significant functional changes.

Note on STEP7:
To use all the functions available up until now, you require STEP7/V5.1+SP3.
The configurations for the corresponding predecessor CPUs are upwardly compatible.

 

The following errors have been corrected:

  • Defect 4550: DA01 in the case of negative overdriving of the analog I/Os
    Even in the case of negative overdriving of the analog I/Os (Ui < -11.75V) no Defect will occur anymore.
  • Defect 4550: FFFF in the case of read DS  / write centrally
    Read DS  / write to centrally located modules is now possible without any problem.
  • Deadlock in the case of decentralized diagnostic alarms and activation / deactivation of slaves
    Incoming diagnostic events from decentralized modules during activation /deactivation of slaves no longer result in decentralized diagnostic alarms not being triggered (no OB82); subsequently, there will no longer be a permanent "faulty" signal in the SZL 692.

Update V1.0.2 (6ES7 314-6CF00-0AB0)

The CPU version does not contain any significant functional changes. 


Note on STEP7:
To use all the functions available up until now, you require STEP7/V5.1+SP3.
The configurations for the corresponding predecessor CPUs are upwardly compatible.

The following errors have been corrected:

  • Defect 4550: 2FFF after power on:
    Defect 4550: 2FFF no longer occurs after power on.
  • SFC 64 "Timetick" sporadically returns arbitrary values.
    In the event of an overflow after 0, SFC 64 now reads the value consistently.
  • Onboard outputs, parameterization +/- 20mA: output in positive range only.
    At the onboard analog outputs, correct values are now also output in the negative range with parameterization of I +/-20mA.
  • At "next statement" at a breakpoint in a jump-to list, there is no jump to the destination mark. Jump-to lists can now be tested without problems in single-step mode.
  • At a breakpoint after "block status", the STA bit is indicated incorrectly.
    At a breakpoint on the first program line of a block, the STA bit is now indicated correctly even after "block status".
  • Routing with the CPU313C-2 DP crashes the communication module of the drives.
    It is now possible without problems to route from the programming device (PG) to a drive (e.g. master drive MC) without the communication module (CBP2) of the master drive crashing.
  • No cyclic data exchange possible with the S7 313C when an S7 slave sends a standard diagnosis (diagnosis length = 6 bytes).
    It is now possible without any problems to activate cyclic data exchange to a master drive slave without the slaving repeatedly having to be reparameterized by the DP master.
  • DP master no longer accepts DP slaves after a bus problem.
    DP slaves are now addressed by the DP master again and added to the ring after bus problems.

 Entry ID:12019198   Date:2009-11-30 
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